mehran1367
Member level 3
hi all , i used report_timing command in design compiler. does it consider the the delay of interconnects and nets to? or the result is just the delay of the cells?
forexample if i use
report_timing -from in1 -to out1
does it consider the delay of the nets ?
i didnt use wire_load command. my technology is nangate 45nm
forexample if i use
report_timing -from in1 -to out1
does it consider the delay of the nets ?
i didnt use wire_load command. my technology is nangate 45nm