While writing the RTL code, we won't be aware of the combinational blocks in the design, right? We will be simply writing the logic to be implemented and we won't be aware how the logic will be implemented. The implementation is done by the tool. Before generating the schematic of the design or before synthesising how can we pay attention to the combinational logic to reduce set up violation? Could there be any coding practice to take care or some other methods?
About hold violation, yeah... I can fix it easily in the PnR stage by adding delays. But suppose the hold violation in my initial netlist is too high. What is the right practice then?? Should I go to the PnR stage to fix it by adding too much delay elements or will I be able to rectify it by modifying my RTL?