Remove padded bytes of zeros

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rac70

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Hi all,
how to remove the extra padded bytes of zeros when every time the bytes of zeros padded may lie b/w 1 to 16 suggest any logic?
 

I suggest you ask a better question....
 

It seems like you are returning to the topic Different widths of data on same bus.

For one thing changing the width is not possible either in simulation or in hardware a bus is a fixed size vector of bits that can't be modified during run time. The width is defined and fixed at elaboration.

So instead of asking how to implement something you came up with that can't be done, why don't you instead state what your requirements are and then ask how it could be done.
 

You could send the data through a state machine, when you see a byte of zero's then you could EITHER switch the mux & essentially drop the data OR just have an enable pin for data valid

Code VHDL - [expand]
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if rising_edge(clock) then
 
  data_valid<= '0';
 
  case state
    when sniffing=>
      if data_byte = (others=>'0') then
        mux_sel = '1';
      else
        mux_sel = '0';
        mux_data_in0 <= data_byte;
        data_valid <= '1';
        state <= tx;
      end if;
    when tx =>
      if rx = '1' then
        state <= sniffing;
     end if;
  end case;
...
 
..
if data_valid = '1' then
   data_in <= data_byte;
   rx          <= '1';
end if;
 

I wonder how you can give a solution for an essentially unspecified problem.

I think the present state of this thread is "waiting for better question" respectively a clear one.

Unless a special coding is assumed, a data byte can be zero, so how do you distinguish it from a padded byte?
 

I see what you mean by valid data being zero's.

I also see what you mean, the question is unclear.
 

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