bitprolix
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I wrote a small FSM (Mealy Machine) transition table design using VHDL and I'm using ISE(Xilinx Design tool) for synthesis. The synthesis goes fine but, It also throws some warning messages. It seems that my code is generating some latches, but I couldn't find a way to remove it.
The input X is the external input to the design which I plan to map using User Constrained file to some switches on my target FPGA board, So should I ignore the first Warning message(shown in bold below). The warning message are shown below.
The complete VHDL code:
Transition table, based on which I've written the above VHDL code is also attached here.
View attachment transition-table.pdf
The input X is the external input to the design which I plan to map using User Constrained file to some switches on my target FPGA board, So should I ignore the first Warning message(shown in bold below). The warning message are shown below.
The complete VHDL code:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lab5fsm is
port (X: in STD_LOGIC_VECTOR(2 downto 0);
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
Y: out STD_LOGIC_VECTOR(3 downto 0));
end lab5fsm;
architecture Behavioral of lab5fsm is
-- define the state of the FSM
type STATE is (A1, A2, A3, A4);
-- signals to manage the current state and next state
signal CURRENT_STATE, NEXT_STATE: STATE;
begin
P1: process (RESET, CLK)
begin
-- Initial state is A1 and the state changes only
-- on rising edge of the clock.
if (RESET = '1') then
CURRENT_STATE <= A1;
elsif (CLK'event and CLK='1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process P1;
P2: process(CURRENT_STATE, X)
begin
case CURRENT_STATE is
when A1 =>
Y <= "0111";
NEXT_STATE <= A2;
when A2 =>
if (X = "00-" ) then
Y <= "1100";
NEXT_STATE <= A3;
elsif (X = "10-" ) then
Y <= "0010";
NEXT_STATE <= A1;
elsif (X = "-10") then
Y <= "1110";
NEXT_STATE <= A1;
elsif (X = "--1") then
Y <= "0110";
NEXT_STATE <= A1;
end if;
when A3 =>
if (X = "-0-" ) then
Y <= "1110";
NEXT_STATE <= A4;
elsif (X = "-1-") then
Y <= "0111";
NEXT_STATE <= A1;
end if;
when A4 =>
if (X = "1--" ) then
Y <= "0111";
NEXT_STATE <= A1;
elsif (X = "0--") then
NEXT_STATE <= A3;
end if;
when others =>
Y <= "XXXX";
end case;
end process P2;
end Behavioral;Transition table, based on which I've written the above VHDL code is also attached here.
View attachment transition-table.pdf