Jan 11, 2007 #1 Y ywguo Junior Member level 2 Joined Jan 9, 2005 Messages 20 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 198 Hi, Guys, How to remove assign statements in synthesized netlist? Some Astro versions do not allow assign statements in verilog netlist. In Advanced ASIC Chip Synthesis, it states that the following command should be set in a script. verilog_no_tri = true set_fix_multiple_port_nets -feedthroughs set_fix_multiple_port_nets -all -buffer_constants I follow the above rule. It failed. Any help is welcomed. Thanks Yawei
Hi, Guys, How to remove assign statements in synthesized netlist? Some Astro versions do not allow assign statements in verilog netlist. In Advanced ASIC Chip Synthesis, it states that the following command should be set in a script. verilog_no_tri = true set_fix_multiple_port_nets -feedthroughs set_fix_multiple_port_nets -all -buffer_constants I follow the above rule. It failed. Any help is welcomed. Thanks Yawei
Jan 11, 2007 #2 J johnma Newbie level 6 Joined Dec 17, 2006 Messages 13 Helped 0 Reputation 4 Reaction score 0 Trophy points 1,281 Activity points 1,340 I resolve this problem by define new naming rules before writing netlist out. Just like this : define_name_rules verilog -remove_internal_net_bus -equal_ports_nets. Also you need the set_fix_multiple_port_nets -all -buffer_constants . Good luck!
I resolve this problem by define new naming rules before writing netlist out. Just like this : define_name_rules verilog -remove_internal_net_bus -equal_ports_nets. Also you need the set_fix_multiple_port_nets -all -buffer_constants . Good luck!
Jan 12, 2007 #3 Y ywguo Junior Member level 2 Joined Jan 9, 2005 Messages 20 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 198 Mission Complished. Thanks.