i just know that
Vin=Z11*Iin + Z12*Iout
so that
Z11=Vin/Iin when Iout=0
i am not quite familiar, i think just plot S11 in smith chart to see whether it's matched or not.
for Z11 i think it's a complex value, the real part of Z11 is the input resistance, i think you can plot the value versus frequency
If z12 is not zero, the input impedance will be different from Z11 if you have a load that is not a short circuit. Usually Z12 is so small that there is little difference for practical purposes between input impedance and z11 unless you are using the active device near the high frequency end of its range.
sorry, i have no experience about that.
but curious about it, seen from the right of Lg1 to the input of the NMOS, it's the gate of MOS and loaded with a 10K bias resistor, i think the real part should be almost 10Kohm.
anyway, what does ZM mean, i never used it.
i think you can also use ZP and check the real part of Z11 instead and see whether it is still negative?
yes, the 10K ohms resistor can be ignored since there is a much smaller impedance in parallel.Why do you think the real part is about 10K ohms? What if the biasing resistor is placed in parallel with capacitive impedance (Cgs). Since Rg1 is far greater than the capacitive impedance, then 10K should have very little affect on over all impedance. right?
yes, the 10K ohms resistor can be ignored since there is a much smaller impedance in parallel.
i have no idea now. hehe
ZPort Impedance.Whe you look through a port, the impedance which you'll see from this port.
ZM:Open circuited Z parameter.It's totally different than ZP because Z12 is not zero.The impedance which you will measure with VNA will be ZP, NOT ZM.
But they are convertible between them.
Wrong, if you mean Post Processing of Cadence Spectre.ZPort Impedance.Whe you look through a port, the impedance which you'll see from this port.
ZM:Open circuited Z parameter.It's totally different than ZP because Z12 is not zero.
The impedance which you will measure with VNA will be ZP, NOT ZM.
Wrong, if you mean Post Processing of Cadence Spectre.
ZP ; Open circuited Z parameter
ZM ; Input impedance seeing from Port.
So the impedance which you will measure with VNA will be ZM, NOT ZP.
Yes.
What do you mean by "output stage" ?
Do you mean output impedance ?
If so, simply your output impedance is dependent on load termination which is Rs in your schematic.
So you have to study source stabilty and load stability.
Yes.
Simply your input impedance is dependent on load termination which is RL in your schematic.
ZM(1)@"RL=inf" = ZP(1,1)
Your circuit could be unstable for RL=50ohm.
So you have to check load stabilty
Also you have to check source stability.
Yes.I just set up the schematic of the circuit in Cadence and run SP analysis.
So ZM should be more accurate than ZP according to how my circuit is set up above?
Simply your input impedance is dependent on load termination which is RL in your schematic.For my output stage, using ZM1, I got negative real part.
If I use ZP, I got positive real part. Don't know why? Any idea?
No.ZM(1)@"Rs=inf" = ZP(1,1)? So ZM1 is defined when impedance of the source is infinite?
If you prefer Cadence Spectre, see figure in The Designer's Guide Community Forum - how to simulate noise matching for LNA in spectre?.How to check load stability and source stability respectively in Cadence? K factor?
Wrong, if you mean Post Processing of Cadence Spectre.
ZP ; Open circuited Z parameter
ZM ; Input impedance seeing from Port.
So the impedance which you will measure with VNA will be ZM, NOT ZP.
See https://www.edaboard.com/threads/166900/
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