Relationship between GPIO output pin load capacitance and drive strengths?

Hi,

A: delay depends on the circuit and how it is defined. I guess no general answer can be given.

1) what is "output capacitance of an input pin"? I don´t understand the statement at all
2) same as 1
3) in most cases: yes

I guess this topic can´t be answered in general. It´s not clear whether you talk about IC design, schematic and/or PCB layout, wiring... Is it a true communcation interface (with it´s standard / specification) or are you talking about general purpose IO (GPIO) (you mix both in your post)

Thus I recommend to give more detailes about your application, so that we are able to focus on the issues.

Klaus

Hi Klaus,
Thank you for the comment. Let me give an example.
Assuming I am connecting a single output from 74LVC8T595 (master) to input of several 74LVC8T595 (slaves).
The datasheet of 74LVD8T595 implies the below -
1. Maximum output load capacitance of 30pF
2. Maximum input capacitance of 3pF
Based on the maximum output load capacitance, the master are able to connect to a maximum of 30pF/3pF=10 slave devices. What happen when we add more slaves?
Assuming it is a clock signal. How do we make a good guess on the max frequency it could run on when more slaves are added?

Some datasheet does not provide maximum load capacitance. Are we able to use the output pin drive strength to determine how many slave we could connect?

Hope this is clearer. Thanks.
Best rgds,
Pang

Some (few) manufacturers give spice models for the GPIO.

More typically some will do something like this :



This is still one of the persistent complaints about CPU datasheets, incomplete DC and AC characterization. And many processors now done in ASIC processes and tools, all which
have this info.

Industry is still not fully transparent after 40+ years of asking.



Regards, Dana.

Hi,

1) where in the datasheet do yo see a "max output load capacitance of 30pF"?
My datasheet (Nexperia) does not show this.
2) my datsheet says "typical" (not max) iput capacitance of 3pF.

Give a link to the datasheet you use.

I don´t understand your schematic how you connect several slaves in parallel to one master. Does it make sense at all?

kakiitek said:

Based on the maximum output load capacitance, the master are able to connect to a maximum of 30pF/3pF=10 slave devices.

Click to expand...

here you forgot the pcb trace and wiring and stray capacitance.

kakiitek said:

What happen when we add more slaves?

Click to expand...

It depends on the wiring.
Basically: The capacitance will increase, propagation delay will increase, the rise/fall time will increase, power disspation will increase, ground bounce will increase...

It depends on your circuit, wiring and timing whether the delay causes problems.
It depens on how many outputs are switching at the same time whether this causes GND bounce problems.
It depends on how many outputs are switching at which frequency whether the power dissipation causes problems.

I see no GPIO, no configurable drive strength.

kakiitek said:

Assuming it is a clock signal.

Click to expand...

Really .. a clock signal feed through a shift register. Good thing the output frequency at Qx in worst case is half of the SHCP frequency.

kakiitek said:

How do we make a good guess on the max frequency it could run on when more slaves are added?

Click to expand...

Best and safe method is to keep on the datasheet and don´t overlaod the output.

kakiitek said:

Some datasheet does not provide maximum load capacitance. Are we able to use the output pin drive strength to determine how many slave we could connect?

Click to expand...

Give a link to the datasheet so we can talk about it.

Klaus

They are related by the rise / fall time that is required. For example a 100Mhz clock would probably want to allocate 1ns to rise and 1ns to fall time out of the 10ns period. Then simplistically the C*(0.8*vdd)/1E-9 ought to tell you the current needed to get the 10-90% edge time wanted.

Bearing in mind PVT yadda yadda.

kakiitek said:

Assuming it is a clock signal. How do we make a good guess on the max frequency it could run on when more slaves are added?

Some datasheet does not provide maximum load capacitance. Are we able to use the output pin drive strength to determine how many slave we could connect?

Click to expand...

Hi,

I'm not sure but I feel you are mixing fanout with odious delay, to put it like that.

More slaves = less drive current to share between them from the driver, to charge the input transistor gates. Like using nC + dV + Ig = t(s) to calculate Rg for a MOSFET gate turn on in the desired time, after all, most inputs are transistor gates or bases. So many things seem to be reduceable to an RC time constant, if lucky the datasheet gives R and C or if not so lucky you are stuck having to extrapolate from Cin and Trise what Rin is maybe probably presumably approximately... Even if it's actually a Zin, Rin is comprehensible when used in this context, I would hope.

If (master) OUTPUT_PIN_ABC source capability is e.g. 1mA and sink capability is e.g. -0.6mA and (slave) INPUT_PIN_XYZ requires +100uA ON and -100uA OFF drive, then when ABC is high, fanout is ten, but ABC low won't be as strong, I guess, and master would struggle to pull all ten slaves fully low. Hope that isn't an idiotic comment.

Another thing is C_input and C_stray, and as already said, calculating current needed to charge input pin at required/desired speed, and maybe there ABC can or can't provide the power to n * XYZs.

So, in my ignorance, I'd agree with the second paragraph of yours I quoted.