Relationship between CMRR and DC offset

[terryssw]

"Just remember that CMRR is an AC manifestation of the DC input offset voltage". - I have heard this sentances serval times before but I don't understand the meaning. Can someone help to give some in-depth explanation in the topic? Thanks in Advance!

 

[RegUser_2]

"Just remember that CMRR is an AC manifestation of the DC input offset voltage". - I have heard this sentances serval times before but I don't understand the meaning. Can someone help to give some in-depth explanation in the topic? Thanks in Advance!

The CMRR = CMG/DIFG where the CMG is the common mode gain of a differential amplifier (both inputs tied together), and the DIFG is the differential gain of the amplifier (signal applied between the two input). Ideally the CMG should be zero, yet due to the missmatch of the diiferential pair component parameters the both arms of a differential pair usually have missmatched gains. Since the DC offset of a differential pair is related to the matching of the components in the individual arms of the pair, then the larger DC offset COULD also be indicative of worse CMRR (not quite valid for systems with strong internal negative feedbacks).

 

[terryssw]

Thanks for your replys. Does there is some mathematical relationship between CMRR and DC offset?

Also, is it right that even we have no DC offset (just ideally says), we still have finite CMRR due to the finite output resistance from the tail current source? So it means that CMRR combine the effects of mismatches of transistors as well as finite output resistance in tail current source?

 

[leebluer]

i agree with terryssw. i also think CMRR is relative to both the effects of mismatches of transistors and finite output resistance in tail current source.
but i am confused about the simulation of CMRR, because in general simulation the mismathches of transistors are not involved, and does it only involve the effects of output resistance in tail current? how can i get more accurate results of the CMRR, i mean to involve the effects of the mismatches.

thanks

 

[terryssw]

I think to simulate the mismatches, Monte Carlo simulations is required with mismatches parameters given from technology foundary.

 

[RegUser_2]

Naturally ANY missmatch lead to worse CMRR. For instance if the current sorces in the source lines of otherwise perfectly matched FETS are missmatched, then we will get both a different VGS what reflects upon different DC offset AND also the transconductances of the FETS will differ, what leads to different gains (non zero CMG).

 

[fehler]

In Laker and Sansen's book, I think there is answer. There
the CMRR is divided into 2 parts, and one of it is related to
dc offset with a equation.

But I am not sure, I have not this book in hand. So please who
can check it? BTW, I think this is a best book.

 

[rajath]

A non-ideal current source will keep altering the bias points, modulating it with the input signal, and hence varying the small-signal gain too. As a result
the output gai nwill have a dependence on the input CM level. Mismatch obviously will result in differentia lgain variation - which can be viewed as common mode gain.
For a rough idea of how much the CMRR will degrade due to mismatch, you can simply use slightly different aspect ratios (maybe +/- 1%) for the two input transistors, or for that matter any components that need to be matched.
I've also heard that PSRR is a manifestation of voltage offset, but haven't quite been able to see why? Any insights on that?

 

[xuanzhu]

CMRR = CMG/DIFG

if this equation is correct, the CMRR will be lower to zero, and this opamp will be a garbage.
the correct equeation is that CMRR=|DIFG/(CMG-DIFG)|