relation btw cmos technology, device model and power supply.

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For CMOS simulation by Hspice. ex. inverter. I found that if we use level one model seems Vdd=5V; use level3 model, Vdd=1.5V. Is there any rules for this? also for tmsc 0.18um technology, seems i should use vdd=1.8V? What's the relationship among the MOSFET model, CMOS technology (0.18um, 90nm technology) and power supply voltage? If I use too high voltage, ex. 5V Vdd for 0.18um technology, what will happen? is it OK?
 

Re: relation btw cmos technology, device model and power sup

The operating voltages are defined by the Digital technologies. For a small channel length device in which the channel length has been shrunk is accompanied by decrease in the gate oxide thickness, so an upper limit to the voltage is defined by that and also some other breakdown voltages, since if you apply too high a voltage then there will be oxide breakdown in a real device and you device model is not valid anymore.
For a nice discussion on this read the Scaling theory note on Desing of CMOS Analog Integrated Circuits by Behzad Razavi, Cahp 16.

The book can be found here:
 

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