relation between the drive strength & delay??????????

[ram007p]

HI all,

can any one clarify this.

if increase the drive strength what happed my delay????????????/

 

[sat]

Delay will reduce.

A cell's drive strength indicates how capable they are to charge and discharge the load cap.
More drive strength means more current capability - means faster charging/discharging of load capacitor.
So, resultant slew will be different at the output of a cell [same logic functionality] with different drive strength.
- How much will the delay be reduced or improved ?
-- That depends on load cap and drive strength. If your load cap is insignificantly low, after increasing the drive strength of the cell - you may not see noticeable improvement in the delay, and, so if you have significant cap load, the improvement after replacing the low-drive-strength cell, with a high drive strength will be quite noticeable.

 

[chuckey]

HI all,

can any one clarify this.

if increase the drive strength what happed my delay????????????/

The drive strength?, voltage? power? from what to what? Happed my delay, You think some delay (from what to what?) changes, can you be a bit more clear with your question?
Frank

 

[FvM]

The drive strength?, voltage? power? from what to what?

Drive strength is a commonly used term with digital logic. It's usually the output current available at maximum allowed output voltage drop for the respective I/O standard. CMOS I/O standards have usually symmetric driver output impedances, so a single number (e.g. 16 or 24 mA) can specify the drive strength. Today's programmable logic (complex PLD and FPGA) have mostly programmable drive strength, e.g. ranging from 2 to 24 mA. It's mainly utilized to control impedance matching and output slew rates.

As logic output delay is referring to a threshold voltage at 0.5 Vcc, it's implicitely affected by slew rate changes. You'll find detailed data in some data sheets or device IBIS models. FPGA timing analyzers can take load capacitance into consideration (e.g. with Altera Quartus) and calculate effective in-cicrcuit delays.