buenos
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hi
i have a bidirectional 32bit bus.
this has to be driven directly from a statemachine, and not from an assign statement. The reason is to decrease the clock-to-output static timing.
In VHDL, this works fine, but in verilog it gives me errors.
If i define the bus as reg, it complains that reg can not be bidirectional, if i dont the it complains about something else.
so, how take drive the bidir bus directly from the statemachine, and how to define the port for that?
i have a bidirectional 32bit bus.
this has to be driven directly from a statemachine, and not from an assign statement. The reason is to decrease the clock-to-output static timing.
In VHDL, this works fine, but in verilog it gives me errors.
If i define the bus as reg, it complains that reg can not be bidirectional, if i dont the it complains about something else.
so, how take drive the bidir bus directly from the statemachine, and how to define the port for that?