kaz1
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This is about timing violations at async reset release. Implementing it and synchronising it is dead easy. but my question is about underlying concepts.
In FPGA vendor or user literatures I find it hard to fully understand the concept of recovery/removal. So Thought may be ASIC designers can shed some light.
Async reset release timing violation relates to sampling window defined as:
Recovery is equivalent to "setup violation at reset release" and Removal is equivalent to "hold violation at reset release".
So it relates to sampling window which originally is meant for D input yet there is no clear discussion on relevance of D input and whether it contributes to the concept or not.
I also read that if the register is going to change internal state due to change (at D input or Q output) then reset release becomes critical otherwise it does not matter.
If so how to reconcile (D , internal state, Q output) as relevant., or is it only D state coinciding with reset release that causes concern?
Thanks
In FPGA vendor or user literatures I find it hard to fully understand the concept of recovery/removal. So Thought may be ASIC designers can shed some light.
Async reset release timing violation relates to sampling window defined as:
Recovery is equivalent to "setup violation at reset release" and Removal is equivalent to "hold violation at reset release".
So it relates to sampling window which originally is meant for D input yet there is no clear discussion on relevance of D input and whether it contributes to the concept or not.
I also read that if the register is going to change internal state due to change (at D input or Q output) then reset release becomes critical otherwise it does not matter.
If so how to reconcile (D , internal state, Q output) as relevant., or is it only D state coinciding with reset release that causes concern?
Thanks