Regd XTAL OSCILLATOR design

[kavithak23]

xtal oscillator

Hi,
I am currently working on XTAL OSC design.

I have certain doubts.

1. The xtal provides 180 phase shift and the inverter provides the remaining 180 phaseshift. What is the contribution of Rf (feedback resistor) in addition to providing DC biasing. Does it provide any additional phase shift?. On what basis the size if chosen?.

2. On what basis the size of the inverter should be chosen. I have seen really big sizes. If gain gets fixed by the Rf (feedback resitor) then what is the need for big sizing of the inverter?.

3. How to measure negative resistaonceof the crystal.

4. Written theory for measuring the gain and the values of the xtal oscillator?.

thsnks&regards,
sridharan

 

[saro_k_82]

xtal oscillator circuit

1. The biasing resistor is not designed to carry the signal current. So it does not have a role to play in phase shifts (meaning it cant change the frequency). It just reduces the differential impedance seen across the crystal., thereby reducing the effect of amplification.
2. The gain does not depend only on the resistor. Increasing the size is to increase the gm to work in the optimum gm region.
The following paper discusses the required theory and the negative resistance of the three point oscillators
High-Performance Crystal Oscillator Circuits: Theory and Application . E. Vittoz et., all

 

[kavithak23]

xtal oscillator design

Hi,

1. The pi network in the oscillator (C1-R1-C2) will contribute to 180 phase shift if crystal is considered separately. But when it comes in the feedback loop, do you stilll say that the transistor sizing/Feedback resistor doesnt contribute anyting to the phaseshift. I mean Crystal series resistance may come in parallel with the effect of the Rf resistor or the output resistance of the resistance.

2. I have the values of R1,CL and Co. Now how will I derive at the Rf(feedback resistor) ad the transistor sizes and the power limiting resistor without actually simulating the circuit. I need a theoretical model for analysis. Can you help with the design guide/equations.

thanks&regards,
sridharan

Added after 1 hours 11 minutes:

Hi,
Also if somone helps in knowing the effect of package RLC on the oscillator circuit, it owuld be appreciated.

 

[saro_k_82]

xtal measure serial parallel

The expression for impedance looking from the crystal is Zc = Z3.(Z1+Z2+gm.Z1.Z2) / {Z1+Z2+Z3+gm.Z1.Z2}, where Z1 and Z2 are the loading caps. Z3 is the impedance that appears across the inverter. You can derive the exact expression for the negative resistance and phase shift at various frequencies that the crystal sees by substituting for the Z's.
You will arrive at the condition for sustained oscillations.
gm^2 + w^2.(C1+C2)^2 < R1.w^2.gm.{C1.C2+2.C3.(C1+C2)}
(C1 and C2 are the two loading caps)
But this is the hard limit., we dont work anywhere near this., Much before the resistor starts to show some appreciable phase shift the phase noise degrades and when you design to meet the phase noise spec, you'll almost never need to worry about the phase shifts the resistor introduces.

The classic paper on the crystal oscillator discusses the optimum gm and many other design criteria.

 

[kavithak23]

xtal feedback resistor

Hi,

I have a few more queries.

The crystal manufacturer specifies the vales of C1,C2 (Load) and the crystal parameters (R,L,C and C0). This would give a particular phae shift (pi network). Now there would be some more additional capacitances like input capacitances, PCB trace capacitances and bond pad capacitances that would be added along with the crystal load, which means that the pahse changes to some other values since the valus of CL gets altered due to these parasitic elements. Now which needs to be adjusted to compensate for the phase errors. I mean where do you have the control to alter the pahse chages in the circuit. Is that phase chages would be adjusted automatically with the feedback loop and nothing need to be done?.

Kindly explain me on this.

thanks&regads,
sridharan

Added after 2 hours 27 minutes:

Hi,
I have one more doubt.

What would be the problem in designing crystal IO for 1.8V,2.5V and 3.3V (Multiple voltage domain). Can I have parallel stack and achive the same Gm?.
can anyone please answer this?.

 

[saro_k_82]

phase shift effect xtal oscillators

The other device and stray capacitances will be small compared to the load capacitances. They reduce the frequency and it is called load pulling., which is given by FL=Fs*sqrt(1+Cm/(Cp+CL)). Where Cm is the motional capacitance, Cp is the package capacitance and CL is the effective load capacitance. With high Q crystals (with small Cm) the pullability is low and the frequency does not move appreciably.

 

[kavithak23]

cm xtal frequency

Hi,
If Rf provides only DC biasing, why is the value varied wrt to Crystal frequency. Iam seeing Rf is inversly proportional to operating frequency. And why are they of huge value. I can provide feedback using a small values resistro since the current at the input of inverter is zero.

How do you come up with the feedback resistor value.


rgds,
sridharan