Regd. Current reference and start up circuit

[srivatsan]

how much the operational characteristics of the current references and the start up circuit is affected by the variations in W/L? books dont detail on its design. let me know some one who has designed these circuits.
p.s.: i am using modified cascode mirror circuit.. it works just fine IF the current references work well... ie the output resistance of the current references should be reasonably high.
thanks in advance
srivatsan[/u]

 

[Fom]

I didn't understand your question. Can you draw schematic?

 

[srivatsan]

i am not sure how to design the start up and current reference nmos transistor W/L. i am sure about their working but how to verify them? kinda not sure.
if there are other alternatives, (without bjt), let me know. thanks in advance.
srivatsan

 

[Fom]

First of all your schematic is wrong. You should mirror 2 NMOS an resistor of current reference. The NMOS of start up circuit should very long-channel transistor, the W/L of this transistor is defined by specs on Icc of this current reference (especially for highest Vcc value). W/L start up PMOS transistors is not so important.

 

[srivatsan]

hi fom,
well i was wrong.. i got the correct circuit... right now, i am simulating it again. it has good stability when there are changes in VDD, VSS.

well, according to what u said, I increased the NMOS channel length by 6x (0.6um) for current refernce and NOT the start up circuit. (is it because of high output resistance needed to be seen in NMOS??).

what about W/L for start up circuits?? Not so important???? let me know

I have attached the new circuit figure.
thanks in advance..

srivatsan

 

[srivatsan]

well, i got a good constant current reference and high stable mirror also. but i could nt simulate the effect of start up circuits... if any has an idea how to simulate it, please let me know.. thanks in advance.
srivats

 

[electronrancher]

you'll need to run a transient sim. VCC should be a voltage pulse that starts at 0, waits 1-2us, then ramps up to it's final value. This transient will catch most broken startups.

DC sim cannot find a broken startup circuit, as spice is very good at converging a bad circuit to a good operating point.

 

[Fom]

For other circuits (bandgap for example) when you simulate start up circuit you should consider transistor mismatch or OP amp offset. But I think your circuit not so sensitive to mismatch. If you simulated it for wide VCC range and it worked - everything is OK.