Can someone tell me how to connect:
Metal 2 to metal 1 (case 1 fig),
Metal 2 layer to Metal 1 layer than to polysilicon (case 2) ?
Metal 2 to Polysilican (case 3 fig)
I knwo that we use Via but I dont know which Via to use since there is Via1, 2....
Hi AdvaRes - I guess the process is indicating that if you are using a wide metal then some process need a multiple rows of vias i.e 10X10 VIA's or maybe that you need a large size of vias but normally large sized VIAs are used in bondpads or IOPADS.
I would suggest that if you used wide metal make a multiple rows and columns of vias, also you can make you wide metal i.e multiple of 4microns wide or so.
Then hopefully your DRC problem will be gone.
I hope this help.
Cheers
AdvaRes said:
Thank you drDOC and analayout,
I agree with you analayout Via 1 is used to connect M2 to M1. My problem is that Virtuoso shows this error message
Rule VIA1X.LO.1: Minimum number of VIAiX inside {VIAiX upsized by 30.0um}: 10
Also, When I zoom out I get a Vertex Polygon arround my layout (a very big square )