Regarding the Uart baud rate support in Spartan 3A FPGA (XC3S400A)

Status
Not open for further replies.

prakashvenugopal

Advanced Member level 1
Joined
Jun 1, 2011
Messages
473
Helped
15
Reputation
30
Reaction score
15
Trophy points
1,298
Activity points
4,973
I am using Spartan 3A FPGA (XC3S400A). what was the Maximum Uart baud rate it can support?
 

I think you can go higher than anyone really wants with an asynchronous UART. I expect the maximum to be in the range 10-100 Megabaud, depending on the UART implementation.
 

A high speed UART can be appropriate as a simple interface between digital systems, e.g. using a LVDS IO standard. For the receiver, you'll need a sufficient oversampling ratio. I'm e.g. using a 40 MBps UART with factor eight oversampling. A suitable system clock is needed too.

When representing standard UART frequencies, there may be a problem to generate the right baud rates. But in FPGA design, you have all options like unusual overampling ratios and fractional frequency dividers. I designed e.g. a 115 kbps UART running from a low 6 MHz clock, using a factor 13 oversampling ratio.
 
Reactions: sanju_

    sanju_

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…