Maitry07
Advanced Member level 4
Hello support team,
I am using 2 different ready FPGA IP cores with different data widths and I want to interface the 1st IP output data continuously with the 2nd IP input. Details as below.
1. Interfacing IP core - 1st IP core, which has a data width of 64 bits with a clock frequency of 15.36 MHz ( 0.0651041 usec) , that means for the single sample(16 bits)- the clock period is 0.0162760 usec ( 0.0162760 x 4 = 0.0651041 usec ) and it is providing continuous data.
2. Arithmetic IP core- 2nd IP core, which has a data width of 16 bits with variable clock frequency selection. So, in order to provide all samples from interfacing IP core output to arithmatic IP core input, If I select the clock frequency of the arithmetic core as 61.44 MHz. then it would be possible for this core to take 16 bits( 1 sample) in 0.0162760 usec.
So, as my interface IP core is providing 0-63 bits ( 0-15, 16-32, 33-48, 49-63 bits ) and my arithmetic core is taking 16(0-15) bits as input width. what should be the suitable option( may be loop) so that arithmetic core can take input in such a manner (0-15, 16-32, 33-48, 49-63 and then again 0-15, 16-32 ....)
I am using 2 different ready FPGA IP cores with different data widths and I want to interface the 1st IP output data continuously with the 2nd IP input. Details as below.
1. Interfacing IP core - 1st IP core, which has a data width of 64 bits with a clock frequency of 15.36 MHz ( 0.0651041 usec) , that means for the single sample(16 bits)- the clock period is 0.0162760 usec ( 0.0162760 x 4 = 0.0651041 usec ) and it is providing continuous data.
2. Arithmetic IP core- 2nd IP core, which has a data width of 16 bits with variable clock frequency selection. So, in order to provide all samples from interfacing IP core output to arithmatic IP core input, If I select the clock frequency of the arithmetic core as 61.44 MHz. then it would be possible for this core to take 16 bits( 1 sample) in 0.0162760 usec.
So, as my interface IP core is providing 0-63 bits ( 0-15, 16-32, 33-48, 49-63 bits ) and my arithmetic core is taking 16(0-15) bits as input width. what should be the suitable option( may be loop) so that arithmetic core can take input in such a manner (0-15, 16-32, 33-48, 49-63 and then again 0-15, 16-32 ....)