Regarding PVT Corner Simulation

[Durga Srikanth]

I am designing the 8 Bit Carry lookahead adder using dynamic circuits which work in GHz. I have done all the 45 corners (pre-sim) files but out of 45, 40 corners have good wave form and functionality correct . But my circuit should be fast . The remaining 5 processes are (SF, FF(0.8), FF(0.72) FF(0.88), SS) while coming to the FF There is wrong functionality in the (Cout, S7, S6, S4, S1) These are the outputs of my CLA Remaining (s5,s3,s2,s0) having correct functionality. coming to the transistor sizing of and p&g generator, sum generator, carry generator has given the same sizing. I want to design high-speed CLA but in the Pvt. SS, SF.FF is the worst case, looking for suggestions to work in all Pvt simulations.

thank you in advance

 

[AMS012]

You should try to see what is failing in those 5 corners. Simulate one of those corners and plot the waveforms starting from the inputs and trace every net to see where the waveform is not as expected. Once you zero down the problem, you will know how to fix it.
This is the general guideline for any digital design.

In your adder, when you have multiple signals coming through different paths (like sum and carry etc.), and you use them for some more processing, it is very much possible that the delays are not the same through different paths and hence the functionality fails. This could be the reason why your adder is failing functionality at FF, though in general, purely combinational digital circuit is very unlikely to fail in fast corners ahead of slow corners.

 

[dick_freebird]

Carry / look-ahead logic is often the "thickest" inter-stage logic especially at the higher order bits.

In the past I have used schemes such as pipelining the slower changing bits to flatten the critical path.