Regarding pattern simulation

[shivakumar043]

Hi all, I am learning dft i have some query relating to pattern simulation any one knows plz let me know

after the pattern generation i saved the patterns in both serial and parallel format. No simulation failure occures for both serial and parallel patterns . I manually inserted a s-a-0 fault on SI (scan in) (by editing the netlist) only serial patterns detecting this fault but parallel patterns just clearning the simulation. I just wanted to know why parallel patterns not detcting this fault....

 

[joe2moon]

Parallel patterns just test the "capture" process, i.e., it applies stimulus on the fan-in cone of each data input pin of register (ex: D-pin) then check the data with capture clock to see if it meet setup time & hold time requirements.

By contrast, serial patterns do shift-in stimulus bit-by-bit through scan input pin (ex: SI-pin) and pass the register's output. It check the "shift" process.
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Parallel patterns are used ONLY for "simulation".
Because it reduces the simulation time a lot. (compared with serial patterns.)

Patterns which used on testers are ALWAYS in "serial".
Because on the ATE, tester cannot apply inputs on internal nodes directly.
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That's the reason why {min-set of "serial" patterns} + "parallel" patterns are usually used for simulation.

min-set of "serial" patterns: verify scan-in -- scan-out paths
parallel patterns: verify functional capture cycles.
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