[SOLVED] Regarding P-TYPE FET not getting Fully OFF problem

[umesh49]

Hi,
I have placed a P-tyep FET to control the power on my board. gate of P type FET is connected to source with 10k resistor, and I am trying to make gate to be floating or low state using an external signal. Source is connected to input power and drain is connected to the input of LDO on the board.
I have two observation to mention;
1. With gate is left floating, I found drain of FET to be at 2V (with 7 V source) and 1.5mA current is flowing through FET.
2. With LDO input is disconnected from FET drain, I am gettnig zero volt at source with uA current flowing (this is what I was expecting even when LDO is connected).

This is quite strange problem for me and when I tested the same FET on differrent board with putting resistive load (instead of LDO) then it is getting turned OFF properly. Please suggest me how I can rectifiy the issue.

Regards,
Umesh

 

[dick_freebird]

Measure your actual Vgs in the "floating" condition, and
measure the current between this "floating" gate and
whatever is usually driving it (perhaps using a shunt
resistor if a current meter would destabilize things; try
both). That ought to point you at the problem.

 

[alexan_e]

1. With gate is left floating, I found drain of FET to be at 2V (with 7 V source) and 1.5mA current is flowing through FET.

can you please disconnect the driver and leave the gate connected only with the 10K resistor to the source, now do you have the same problem as before?
If not then you driver circuit is responsible for the "wrong" behavior.

Alex

---------- Post added at 23:08 ---------- Previous post was at 23:00 ----------

From the behavior you describe i assume that your driver does not turn off the mosfet completely
and because of the state of the mosfet you have a high drain source resistance.
The difference of the drain voltage is because the resistor and ldo behave differently as loads.

Alex

 

[umesh49]

Thanks for your response.
I have tested the FET when its drain is not connected to LDO and everything looks fine. There is no voltage appearing at drain. So I made one more observation(in the same order) as;
1. Make the supply to the drain ON, with gate is connected to source with 10k. No voltage is appearing at source
2. Make the gate grounded, full voltage appeared at regulator input (at source of FET)
3. Left the gate floating again (connected with 10k with drain); Now 2V is appearing at drain
4. Short (with less than 50 Ohm resistor, more will not work) the input or output(10uF) capacitor at LDO input/output, again the drain voltage disappear.

I am clueless what this LDO and capacitor are doing with the FET and it is not getting turned off.

 

[alexan_e]

1. Make the supply to the drain ON, with gate is connected to source with 10k. No voltage is appearing at source

I don't understand what you mean by that, the source is connecter to the positive supply and the output is the drain, so what do you mean by "drain on and source has no voltage"?

2. Make the gate grounded, full voltage appeared at regulator input (at source of FET)

Normal behavior for a mosfet

3. Left the gate floating again (connected with 10k with drain); Now 2V is appearing at drain

Do you actually disconnect everything from the gate (all connections) except from the resistor to the source?

4. Short (with less than 50 Ohm resistor, more will not work) the input or output(10uF) capacitor at LDO input/output, again the drain voltage disappear.

Maybe the voltage in the drain is because the capacitors are still charged, doest it stay like that for long?

Alex

 

[mvs sarma]

i don't think that it is possible to switch off a MOSFET completely.
see by connecting a shortest link between gate and source(close to the body of mosfet. even then that small current would be there. please study the properties off MOSFETs from any datasheet

 

[FvM]

1. Make the supply to the drain ON, with gate is connected to source with 10k. No voltage is appearing at source

You are talking about a PMOSFET? Supplying a positive voltage to the drain sets forward bias to the substrate diode, so the source will get positive as well. Either the description or the circuit is wrong.

 

[LaszloF]

If possible please attach your (complete)schematic, i am very curios about the floating gate with 10k.