Re: regarding output of ip core cordic 6.0
hi,
after generation of the ip cordic core in the sin and cos mode , i used the inbuilt simulation test bench written in ieee encrypted vhdl that was generated alongwith .
i set this test bench module as the top level , and then clicked on run behavioral simulation .
i got the waveform output where i cant understand
1)where is the input phase given
2) where am i getting the output sin and cos values of the input phase .
3)Also , i don't understand vhdl language so i cant understand the code for the cordic.