regarding output of ip cores cordic 6.0

[tanujaguha]

regarding output of ip core cordic 6.0

i generated the ip core cordic 6.0 and made the simulation test bench as the top level module.
but after running behavioral simulation , i cant understand the output waveform . i used the cordic in sin and cos mode.
can someone please help ?

 

[KlausST]

Re: regarding output of ip core cordic 6.0

Hi,

maybe you should describe
* how you tested it
* what you expected
* what results you´ve got

Klaus

 

[tanujaguha]

Re: regarding output of ip core cordic 6.0

hi,
after generation of the ip cordic core in the sin and cos mode , i used the inbuilt simulation test bench written in ieee encrypted vhdl that was generated alongwith .
i set this test bench module as the top level , and then clicked on run behavioral simulation .
i got the waveform output where i cant understand
1)where is the input phase given
2) where am i getting the output sin and cos values of the input phase .
3)Also , i don't understand vhdl language so i cant understand the code for the cordic.

 

[dpaul]

Re: regarding output of ip core cordic 6.0

Please read the Xilinx docu carefully. Everything is well explained there.
https://www.xilinx.com/support/documentation/ip_documentation/cordic/v6_0/pg105-cordic.pdf

1)where is the input phase given
2) where am i getting the output sin and cos values of the input phase .

Have you realized that data is fed in and fed out in the form of AXI-Stream protocol?

3)Also , i don't understand vhdl language so i cant understand the code for the cordic.

If you want to an user level implementation of the IP core, you don't need to understand how the computation is internally done. But you should understand how the core behaves. And you get this info from the IP core documentation.

 

[tanujaguha]

Re: regarding output of ip core cordic 6.0

These are the steps that i follow exactly:
1) generation of the ip core cordic in the sin and cos mode.
2) I set the testbench of the cordic as the top module and then click on run behavioral simulation.
3) The output waveform that i get is as shown below:


However , as mentioned in the core product guide , the cordic in sin and cos mode would give an output which will be the sine and cosine of the input angle given.
But as i see in the waveform , m_axis_dout_tdata_real ,m_axis_dout_tdata_imag,m_axis_dout_tdata_phase are all zeroes throughout.(which according to the documentation, are supposed to be the output)
Also , what exactly is represented by the last two values of ip_cartesian_data and ip_phase_data. I have also attached the elaborated images for the same.
I was expecting an output as given in the mentioned link :
I understand that this link displays the output waveform according to the core version 4.0 , and my version is cordic 6.0, but still I was expecting something similar to the image attached below(taken from the same link mentioned above).

Where can i find the input phase and the output values of the sine and cosine in the waveform that i got after simulation?

 

[dpaul]

Re: regarding output of ip core cordic 6.0

I have never used this IP core so not an expert on it.
But this core should be having some latency. Please refer to the docu.
You must run the sim long enough to exceed the latency period.