regarding multiple clock

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venkatramanan

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I am having multiple clocks..how to handle those clocks?
how i have to manage those clocks?
can u any one explain me...
 

Hai venkat,
For managing two clock u can define like this sdc file...

EX;-
create_clock -name "firstclock" -add -period 2.0 -waveform {0.0 1.0} [get_ports firstclock]
create_clock -name "secondclock" -add -period 2.0 -waveform {0.0 1.0} [get_ports secondclock]

or else u are asking about how to manage the clock timing in STA?????? .. I cant predict the question??

This may help...... Thanks :razz:
 

when you have multiple clocks, one question rise asynchronous or not?
 

how to manage the clock timing?

---------- Post added at 13:32 ---------- Previous post was at 13:31 ----------

not synchronous
 

Hai venkat,

Clock timing depends on the specification file... Also additional to that if u have problem in timing analysis....

EX:- Consider u are having a negative slack in clock path....

If so add buffer deletebuffer upsize downsize etc... to meet the timing


This may help...
 
Also , I will recommand you to use global clock lines for routing the clock........with BUFG ( global buffer) .....how ever there will be skew but mostly will be in limits..... Also put some RLOCK constraints in UCF /SDC file....

Good Luck
 

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