Regarding Memory redundancy

Can any one tell me about memory redundancy?
--How can decide how much redundancy column/row required for memories?
--How can be impact on model a memory in case of this?
-- How do we know is this required?
-- How can we take care of it in behavioral model?
-- I know about redundancy is that? If there are column redundancy is there it means extra column is there in memory , so if fault occurred to the memory the fault column is replace by redundant column.

Redundancy is decided on the following
a) Yield : The foundry will give a model for how memory bit cells can fabbed in one collection and how the yield changes as you increase the number of bitcells. Beyond a point the yield goes down. So you will need to have redundancy columns/bits there.
b) Bit Cell : Bit cells with very small footprint have more yield loss so they need redundancy.
c) Timing of the memory : Most of the memories are without redundancy if the timing is met. Adding redundancy adds to area and complexity in timing. The biggest issue against redundancy is testing, because to enable redundancy....testing needs to be done and software has to change the code to access the redundant columns.

Redundancy is a circuit level implementation so whatever circuit changes you make to enable this has to be modeled in the Verilog/lib/lef....it is a new design

An ECC-capable memory controller as used in many modern PCs (mostly medium- to high-end workstation and server-class) can detect and correct errors of a single bit per 64-bit "word" (the unit of bus transfer), and detect (but not correct) errors of two bits per 64-bit word.

Hamming code is typically used although some use triple modular redundancy. The latter is preferred because its hardware is faster than Hamming error correction hardware