[SOLVED] Regarding for loop in verilog

Status
Not open for further replies.
D

dhivya34

Junior Member level 1
Joined
Aug 7, 2012
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,399
Hi,

When I use the normal for loop in verilog with the loop variable declared as a wire I get the following error
'i' is an invalid type in Generate loop. Must be a genvar

Hence I changed the loop variable i as genvar. I got the following error.
The for-generate loop scope genblk1[2] already exists

Help me fix this!
 

declare i as integer

ex: integer i;

for(i=0; i<x; i = i+1)
begin
end
 

u need to put the for loop inside always or initial block.
 
Reactions: ruwan2

    R

    ruwan2

    Points: 2
    Helpful Answer Positive Rating
Thanks.
But then also I got error.
The function of for loop in my code was to assign values to different bits of the same variable according to some rule.
Hence I had to enclose 'for' within a generate block and name the block to get rid of the error.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…