[SOLVED] Regarding for loop in verilog

[dhivya34]

Hi,

When I use the normal for loop in verilog with the loop variable declared as a wire I get the following error
'i' is an invalid type in Generate loop. Must be a genvar

Hence I changed the loop variable i as genvar. I got the following error.
The for-generate loop scope genblk1[2] already exists

Help me fix this!

 

[sakthikumaran87]

declare i as integer

ex: integer i;

for(i=0; i<x; i = i+1)
begin
end

 

[yourcheers]

u need to put the for loop inside always or initial block.

 

[dhivya34]

Thanks.
But then also I got error.
The function of for loop in my code was to assign values to different bits of the same variable according to some rule.
Hence I had to enclose 'for' within a generate block and name the block to get rid of the error.