Regarding cross talk violation

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Manochitra

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hi....

What is cross talk?? ..........How can we avoid??...... How double spacing will avoid cross talk?
 

Crosstalk is an acronym definition of undesirable interference which causes inducion of signal from a channel to another.
Due to energy propagation dacays inverselly to distance, you can avoid effect routing tracks faraway.

+++
 

Crosstalk is a type of noise generated due to interconnect capacitances between two wires/nets in a circuit.

There are various methods to overcome them.

Double spacing is one technique where we can avoid the interconnect capacitance to a greater extent. Also by using shield between nets.
 

Crosstalk is phenomenon in which switching on a signal net effects switching activity of a nearby net due to capacitive coupling between two nets. Due to process-technology scaling, the spacing between adjacent interconnect wires keeps shrinking, which leads to an increase in the amount of coupling capacitance between interconnect wires. Hence, increase in the crosstalk effect. Crosstalk can severely effect timing in VLSI circuits. Cross-talk has two effects.
1.Crosstalk delay 2. Crosstalk noise
If if two adjacent wires are switching in opposite direction it will slow down signal hence violating set up time. If two net are switching in same direction it will aid timing. This is called crosstalk delay.This is random phenomenon. It depends on switching.
If one net is switching and other is at constant value. The switching one net can cause induce voltage spike on other net. This is called crosstalk noise.

Methods for minimizing crosstalk:
1. Shielding of victim net by VDD/VSS line.
2. Upsize driver of victim net or downsize driver of aggressor net.
3. Add buffer on victim net.
4. Increase spacing between two nets. This will reduce coupling capacitance between two nets.
 
How does upsizing victim or downsizing aggressor reduce crosstalk ?
 

jeet_asic said:
How does upsizing victim or downsizing aggressor reduce crosstalk ?
Click to expand...

Hi Friends,

scenario like this :

one Aggressor and one Victim net(M1) in between coupling capacitance(C).

Setup case:Both are in Opp direction cases delay--Agg is switching from 0 to 1 and Vic is switching from 1 to 0 : total cap = -VDD (0-VDD= -VDD)
NOW-- Agg is switching from 1 to 0 and Vic is switching from 0 to 1 : total cap = VDD (VDD - 0= VDD)
it means now capacitance has to charge from -VDD to +VDD it will take more time cases delay.SetUp is violating.

SOLUTION : Up sizing the vic cell means ur making signal fast,So compare to previous case now it will take less time to charge -VDD to +VDD.

If any thing is wrong correct me

Thanks
 

Hi all,

Assuming, we know the difference between the Crosstalk Delay & Corsstalk Noise.

In case of Crosstalk Noise:
scenario will be like, aggressor net is in transition (or switching) & victim net is in steady state (constant value).

In this case, upsizing the driving cell of the victim net or downsizing the driving cell of the aggressor net will help in reducing the Crosstalk Noise effect.
Since, Crosstalk Noise value depends on the Coupling Capacitance value between aggressor & victim nets and the Ground Capacitance value of the victim as well.

As we know, Crosstalk Noise means Glitch which is formed/induced on victim net which changes the logic value.

The magnitude of this Glitch depends on the following factors.

1. The charge induced by the Coupling Capacitance. More the value of the Capacitance more the charge & more the Glitch magnitude.
Sol: Decreasing the Coupling Cap value will help in reducing the effect.
2. Smaller Ground Capacitance on victim net, faster charging of this cap, implies magnitude of the Glitch will be more.
Sol: Increasing the Ground Cap value will help in reducing the effect.

One more point to add:
We should not try to fix the Crosstalk Noise & Crosstalk Delay effects, as we do in setup & hold violations. We should try to decrease the Coupling Capacitance value & its effects in one or the other manner.

regards,
Subhash C
 


Hi all,

Upto now, we discussed about Glitch Magnitude only.
Can we think of Glitch Width as well?
On what factors it will depends? How it will effect the desing?

It would be good, if you share this information as well.
thanks..

regards,
Subhash C
 
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