Regarding Clock Latency and Skew?

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RGR

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Hai everyone

In my project , at cts stage , after clock routing

Trail 1:
clock skew : 100ps
clock latency :600ps


Trail 2:
clock skew : 200ps
clock latency : 400ps


Which trail is better and why?

please help me.I am using ICC and encounter tool


Thank you

RGR
 

Hi RGR,

The trial 1 and trial 2
it depends upon following
1. what is your block size.
2. Power requirement of the block.
3. CTS structure to TOP clock structure.
...
 

Maybe you need to check for timing performance. Only then you will be able to decide.
 

you should also check:
1- number of the number of buffer added by the post cts setup fix
2- number of the number of buffer added by the post cts hold fix
 
Reactions: ivlsi

    ivlsi

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I think skew should be having more priority .. which is very much important to meet. check your design specification for skew and latency limit.
 

you should also check:
1- number of the number of buffer added by the post cts setup fix
2- number of the number of buffer added by the post cts hold fix
Click to expand...

Could you elaborate please (explain in details)?
 

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