regarding clock gating violations

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Which way of clock gating are you using? latch free or latched one?
Generally in latch free clock gating we get violations because of unnecessary changes in enable within a clock cycle.
So recommendation is to use latched clock which latches enable for entire clock period.
If you are already using latched clock than check if enable stable during rising/falling edge(to avoid setting/hold time violations)
refer the image shown below:

 
hi
is it necessary to get warnings in check timing report if AND gate is used as a clock gating element?

but yes i am getting CLOCK GATING HOLD CHECK FOR THE INPUT PIN... But warnings? is it necessary?
 

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