[SOLVED] Regarding cascode stage with resistive load

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petelee

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The attached is from the book, "Analog design essentials". Slide number is 0251.

Could anybody know how to get the RLc=gm*rDS*RB?
 

When You consider dc small signal MOS model (rds parallel to gm controlled by voltage drop on Rb) You will obtain this expression.
 

Dominik Przyborowski said:
When You consider dc small signal MOS model (rds parallel to gm controlled by voltage drop on Rb) You will obtain this expression.
Click to expand...

Hi Dominik,

Could you explain with the procedures of equations to get the RLc expression? I still have no idea.
Thanks~~
 

Hi shadow222

I think RLc = Rout of cascode = Rout
Rout = Rout_up || Rout_down
Rout_up = RL
Rout_down = rds + gm*rds*RB (gm*ds is gain from nmos to RB)
Rout_down = rds*(1 + gm*RB) = rds*gm*RB (since gm*RB >>>> 1)
----> RLc = RL || gm*rds*RB
From this point I think to get RLc = gm*rds*RB the author assume RLc << RL
----> RLc = gm*rds*RB

- - - Updated - - -

Hi shadow222

I make mistake typing in the end. The author assume RL >> gm*rds*RB not RL >> RLc
 

Hi,

tompham, thank you for your answer. It is clear for me now how RLc is found.
What I still don't fully understand are the two curves in the photo presented by petelee.
Why is ids increasing with RL (until RL_c) and why is iL decreasing only after RLc?

Thank you,

C.B.
 

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