REG case statement in verilog

[samuel_raja_77]

case within case

1.can we use a case statement within a case statment like the one described below
e.g.
case(state2)
1:begin
case(state1)
1:begin
end
2:begin
end
endcase
end
endcase
2.will it be synthesizable and i am using this code for fpga design .......and will there be any back end problems if so what is the solution

 

[bansalr]

case statement in verilog

This is perfectly alright.

 

[spauls]

verilog syntax case statment

there should be no problem in back end. I beleive!!