Reference voltage for SAR ADC and comparator resolution

[AOQ]

offset-voltage gain adc preamp comparator

Dear all :

I am designing a 10b single-ended, charge redistribution type SAR ADC in 0.35um CMOS.
Supply voltage is 3V and power budget is 100uW.
Conversion rate is 10~100KSPS.

I hope to achieve rail - rail input range, thus I need a voltage near VDD/2 for the preamp of comparator, for proper input common mode range.

My question is, in order to save power, i dont want to design a bandgap on chip. Since this voltage is just applied to the gate of preamp , is it suitable if I simply use two large caps (like 5pF) as a voltage divider to generate VDD/2 durning sampling phase ?

If not, is there any method to achieve rail-rail without using offchip reference ?

Another question, as far as I know, comparator offset does not affect the linearity, offset cancellation is not necessary. So why should we design a comparator using two low gain preamps instead of high gain one ? for higher resolution ?

What is the main parameter to determine comparator resolution ?
From simulation, a single dynamic latch without preamps can tells the difference about 0.1 mV !? It seems impossible ....
Should I do the overdrive test to see the resolution of my comparator for
SAR ADC?



Big thanks

 

[selina_wch]

change reference voltage of comparator

The reason of using two preamps is for high speed.normally gain of the first stage is a bit smaller. Gain of the second stage is larger.

 

[AOQ]

site:www.edaboard.com aoq

The reason of using two preamps is for high speed.normally gain of the first stage is a bit smaller. Gain of the second stage is larger.

thx for answering.

so the resolution of comparator is related to the operation speed ?

Thx.

 

[Karthikeya]

comparator resolution simulation

Hi,
To your first question....if your reference voltage is VDD then your comparator design would be very difficult because when the input voltage of comparator is Vdd , preamps go into linear region while the other input is sitting at Vdd/2. Instead a simpler solution would be to use some technique to scale the input to ADC by a fraction and use that in charge-redistribution network...with this the comparator design would be much simpler.
To Second question...any supply jerks or ripples would cause severe distortion in you r conversion. The digital outputs will be corrupted and cannot be corrected later....remember your LSB size is ~3mv.

regards

 

[selina_wch]

sar adc comparator

hi,

Dynamic comparator such as latch can work at high speed, while the its resolution is weaker than static comparator. But 0.1mv difference is not hard for dynamic comparator.