Reference VHDL constants in Verilog

Lucian Mru · Nov 22, 2013

Hello !

I just started using verilog and I want to use constants defined in an VHDL package inside a verilog test-bench. I'm not even sure if that is even possible. Any hint would be appreciated.

I'm using Cadence® Incisive® Enterprise Simulator.

Thanks!
Lucian

FvM · Nov 22, 2013

Write a VHDL wrapper component that returns the constant values as output signals. It can be instantiated in the verilog testbench.

ahmad1954 · Nov 24, 2013

in verilog with `include you can enter a file to your design.

Reference VHDL constants in Verilog

Lucian Mru

Newbie level 2

FvM

Super Moderator

Lucian Mru

ahmad1954

Full Member level 4

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Reference VHDL constants in Verilog

Lucian Mru

Newbie level 2

FvM

Super Moderator

ahmad1954

Full Member level 4

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