refer any memory location in terms of variables.

[adityarajrulz]

i have a memory element as : reg [7:0] memory [0:1000] with data fed into the memory after reading from a .bin file .

if i have to read any memory location say

i. location no 3 , then i can do it by writing memory[3] or memory[2'b11]
ii. location no 15 as memory [15] or memory[4'b1111]

but if the memory location is given to me in variables containing each bits. as b1=1 , b2=0, b3= 1 ................

i mean that all the memory location bits is not known to me and is coming to me in some variables as b1,b2,b3,b4......
then how should i refer to that memory location as memory[4'b b1b2b3b4] or memory[4'b b1,b2,b3,b4] is showing syntax error..

WHat is the proper syntax

 

[FvM]

Sounds like you are asking for a Verilog concatenation operation {b1,b2,b3,b4}.

 

[AlvaroJ]

Sounds like you are asking for a Verilog concatenation operation {b1,b2,b3,b4}.

That's right. Just concatenate your set of variables into one single variable (wire or reg) and use it to address your array. Some simulators and compilers require to first assign the concatenation to a variable, while others will allow you to include it directly in the array: memory[{b1,b2,b3,b4}]. The 4'b-something is only for constants.

 

[adityarajrulz]

thanks for your earlier help.
Due to some reason , I am switching over my code from Verilog to VHDL.

Can you kindly help me as to how to do this because
syntax like

array({b1,b2,b3,b4}) doesnt seem to work!!!!!.

 

[alexan_e]

The concatenation operator in VHDL is &

https://vhdlguru.blogspot.gr/2010/03/concatenation-operator-in-vhdl.html