Reduce power: reduce Freq or reduce volt?

[davyzhu]

Hi all,

How to reduce power?

You have a circuit operating at 20 MHz and 5 volt supply. What would you do to reduce the power consumption in the circuit- reduce the operating frequency of 20Mhz or reduce the power supply of 5Volts and why?

Any suggestions will be appreciated!
Best regards,
Davy

 

[eda_wiz]

dynamic power is proportional to frequency and square of voltage .. So reducing voltage reduces power exponentially rather than linearly incase of frequency

 

[eeeraghu]

Hi,

There r few techniqes to reduce power at various levels, i.e dynamic power, as static power is not in our hands.

And this dynamic power depends on the voltage and switching activity. So at architecture level make sure that few modules work while other modules need to be inunworking stage so that voltage do not pass through these modules and seperate the clock using modules with the other one as the switching activity of the clock is constant and even make use of gray code style in some of the modules, and also gated clocks if possible.

Bye
take care.

 

[anjali]

How to reduce power?

You have a circuit operating at 20 MHz and 5 volt supply. What would you do to reduce the power consumption in the circuit- reduce the operating frequency of 20Mhz or reduce the power supply of 5Volts and why?

Davy

reducing operating freq will redice the power but low speed circuits are not use.
so without reducing the operating freq, power consumption can be reduced by different techniques like clk gating, multi Vdd design etc..

actually power consumption is proportional to the square of supply voltage. so low supply voltage cells need to be used.for this we have to use low power design libraries which can provide low Vdd cells.

 

[AlexWan]

Why not consider to modify the architecture of design to reduce the power consuming?
The frequency or voltage of one design is fixed. Those data are from customer. There are many papers of discussing the low-power though new architecture.

 

[arunragavan]

well dynamic power consumption is a major problem as the fact that Pdyn = CL * Vdd^2

here Pdyn is proportional to square of the supply voltage.. yes reducin he frequency will reduce the power consumption.. but low speed circuits arent considered nowadays.. the agenda is to have high speed low power consumption circuits.

as mentioned there are several impt components in power dissipation.

the impt parameters in power disspation are

switchin component - Pswitch

here Pswitch = CL * Vdd * V * aplha(0-1) * Fclk

here V - voltage swing. - the voltage swing can be reduced to achieve low power constraints.

Fclk - frequency of operation.. this Fclk is an impt element when it comes to switching activity.

Then the impt contributer to power dissipation is short circuit power.. this is a condition when there is a direct contact i.e there always exists a low resistance path between Vdd and GND.. here both the PMOS and the NMOS would be on.

this condition has to be avoided.

Ps-c = Is-c * Vdd^2

The next contributer is the leakage power.

Leakage power is mainly due to reverse bias currents and sub threshold effects.

Pleak = Ileak * Vdd^2

and the most import factor is static power dissipation.

Pstatic = Istatic * Vdd^2

Static power dissipation is mainly due to pseudo NMOS configurations which can be encountered in the circuit.

Here switching activity and shortcircuit effects are due to dynamic power consumption.

there are several methods to achieve low power -

1: ) Clock gating
2: ) Signal Gating
3: ) Adiabatic Computing - controlling the Vt.
4: ) Use of low power busses - use of low swing busses.
5: ) Avoiding CMOS floating nodes.
6: ) Efficient clock distribution.
7: ) DVS - dynamic voltage scaling - This is mainly on the compiler side. where the efficieny of the compiler is exposed / low power design. -adjusting the voltage limits.
8: ) Use of low power RAM cells. -nT RAM Cells.
9: ) Asynchronous Design - effective and efficient when coupled with low power design.

Best results of low power design can be achieved

1: ) reducing the Vt
2: ) Reduced voltage swings
3: ) controlling the on resistance of the device.
4: ) frequency reduction to a certain extent.. but it doesnt always help - as low speed circuits arent prefered.

hope this helps..

any sugessions and corrections welcome.

with regards,
arun

 

[jinsin]

Someone can tell the relevant articles materials or website of digital power management??

Thanks in advance
Best regards,jinsin

 

[sumit_techkgp]

It depends ur requirement. If u r reducing frequency then u can reduce Vdd