Reduce parasitic capacitance

[stanislavb]

Hi,
I need reduce parasitic capacitance for long traces- about 500mm.
We did follow
a.Reduce trace width according existed technology technology - 2.5 mil
b.Make ground plane as far as possible
c.Instead solid ground plane using grid.
The PCB stack up as follow
1.CS
2.Digital PLANE
3.Digital signal
4.Digital signal
5.Digital PLANE
6.Digital PLANE
7.Analog PLANE(power)
8.ANALOG GND
9.ANALOG TRACE
10.ANALOG TRACE
11.ANALOG TRACE
12.ANALOG TRACE
13ANALOG GND
14.Analog PLANE(power)
15.digital PLANE
16.digital PLANE
17.digital Signal
18.digital Signal
19.digital Plane
20.PS

We are interesting to reduce parasitic capacitance for ANALOG TRACES layers. These traces referenced to ANALOG GND layers. What is yours recommendation?
What do you think if we add two solid metal layers connected to nothing between 8 and 9 layers and between 12 and 13 layers. This layer will service as shield for electromagnetic field.
Thank you

 

[marce]

Not a good idea to have unconnected planes. analog traces on layers 10 and 11 should have minimum capacitive coupling to gnd, at 20 layers you have some thin dielectrics compounding your problem!
Another thought, look at the materials you could use for the stack up.

 

[FvM]

The question isn't clear. At first sight, you try to reduce capacitance of analog traces against it's related ground. If so, that's nothing that can be achieved by a shield.

Besides smaller traces, the most important means to reduce capacitance is using thicker substrates/prepregs. Some low Er substrates can be used in hybrid multilayer designs with FR4, but I doubt it's a realistic option for a 20 layer stackup.

I don't get the purpose of the "grid instead of solid plane" point. Either the grid will be dense enough to keep the ground plane shielding effect, then the capacitance won't be reduced. Or the ground plane isn't acting as a real ground plane.

Having 4 analog layers without intermediate ground planes means a lot of mutual coupling.

For low frequencíes (e.g. < 10 MHz) active driven shields may be an option to reduce effective capacitance.

 

[stanislavb]

Hi,
Yes, the frequency is low = 900kHz. Could you explain me what is "active driven shields"?
Thank you

- - - Updated - - -

Hi,
What is idea behind "minimum capacitive coupling to gnd"?
The frequency we are working is 900kHz and this is pure sinus for all conductors.
The difference from conductor to conductor is only phase shift between them.
Thank you

 

[FvM]

Driven shield (or guard) uses a +1 buffer to drive the guard potential from the signal itself. The problem is that the buffer phase lag causes a negative input impedance component around it's corner frequency which can lead to ringing or even instability.