reduce number of flip flop

Status
Not open for further replies.
S

siasia

Newbie level 1
Joined
Jul 26, 2014
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
7
How can i use ROM/RAM for reducing register in VHDL ?
any reference ?
 

That is a very vague question. You can only use ROM/RAM if a suitable application exists. They cannot just replace logic and registers.
DO you have a ram that is being generated with logic? that usually means poor design at the code level. Why not post your problems and the code that causes them?
 

As an example...supose you have an algorithm that requires 1024 register. You need to access all 1024 registers every clock cycle, in this case they need to be registers. If instead you only need accees to 4 of the registers each clock cycle you coud implement the design as 4 memories that each have 256 of the register values.

Regards
 

A FF or register is equivalent to a 1 bit memory. How you need to access this memory depends on how you design your sequential or combinational state machine as serial or parallel bits.

Since RAM is higher density than an array of FPGA macro-cells of registers, choosing a byte-wide or word-wide state machine might be more economical using RAM/ROM memory than single FF registers.

Finite State Machine "Byte wide" design theory will help you implement parallel register implementations..

I believe it is called "One Hot" method . **broken link removed**
 
Reactions: siasia

    S

    siasia

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…