[SOLVED] reduce clock cycle and use it in another block

muzammil007 said:

Hey Guyz,

I am a newbie in the world of FPGA and HDL. I am using verilog as my HDL to code.
I am facing a problem. I am using a clock of 50 Mhz in my design and using clock divider I am reducing my clock to 1Hz.
Now the problem is want to connect this 1Hz output to my counter which I have designed( it counts from 00 to FF) and then I have
a hex to seven segment decoder which takes this count and displays it in seven segment.
How do I connect all these three blocks i.e. clock divider, counter and decoder so that my seven segment can display from 00 to ff.
If anybody needs the code, I can provide it if somebody can help me with the code.

Regards
Maxx

Click to expand...

mrflibble said:

My bad, you are right. I am blind.

In which case, post your full code so far. If you do, see this:

If all you need is connect your modules together, see that link aruipksni posted: https://www.asic-world.com/verilog/syntax2.html

Specifically the part "Modules connected by name". That should explain how to connect things.

Click to expand...

Code Verilog - [expand]
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module clock_divide(clk_out,clk_50);
input clk_50;
output clk_out;
reg[24:0] count; // to count 25 million you need 25 bit counter
reg clk_out;
parameter TC=25'd25000000-25'd1;
 
initial begin
count=0;
clk_out=0;
end
always @(posedge clk_50)
begin
if (count==0)begin
count <=TC;
clk_out <=~clk_out;
end
else
count<=count-1'b1;
end
endmodule
  
//module up_counter( out, enable , clk, reset     );
 
 
 output [7:0] out;
input enable, reset, clk;
reg [7:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin
  out <= 8'h0 ;
end else if (enable) begin
  out <= out + 1;
end
endmodule 
 
// hex to seven segment decoder
 
module hexadecimalcounter(hex_1, hex_0, hex_num);
input [3:0] hex_num;
output[6:0] hex_1;
output[6:0] hex_0;
reg [6:0] hex_1;
reg [6:0] hex_0;
always @(hex_num)  
begin
  case (hex_num)
     4'h0: {hex_1, hex_0} = {7'b1111111, 7'b1000000};  // 7-seg for 0
     4'h1: {hex_1, hex_0} = {7'b1111111, 7'b1111001} ; // 7-seg for 1
     4'h2: {hex_1, hex_0} = {7'b1111111, 7'b0100100} ; // 7-seg for 2
         4'h3: {hex_1, hex_0} = {7'b1111111, 7'b0110000} ; // 7-seg for 3
         4'h4: {hex_1, hex_0} = {7'b1111111, 7'b0011001} ; // 7-seg for 4
     4'h5: {hex_1, hex_0} = {7'b1111111, 7'b0010010} ; // 7-seg for 5
     4'h6: {hex_1, hex_0} = {7'b1111111, 7'b0000010} ; // 7-seg for 6
     4'h7: {hex_1, hex_0} = {7'b1111111, 7'b1111000} ; // 7-seg for 7
     4'h8: {hex_1, hex_0} = {7'b1111111, 7'b0000000} ; // 7-seg for 8
     4'h9: {hex_1, hex_0} = {7'b1111111, 7'b0011000} ; // 7-seg for 9
     4'ha: {hex_1, hex_0} = {7'b1111001, 7'b1000000} ; // 7-seg for A
     4'hb: {hex_1, hex_0} = {7'b1111001, 7'b1111001} ; // 7-seg for B
     4'hc: {hex_1, hex_0} = {7'b1111001, 7'b0100100} ; // 7-seg for C
     4'hd: {hex_1, hex_0} = {7'b1111001, 7'b0110000} ; // 7-seg for D
     4'he: {hex_1, hex_0} = {7'b1111001, 7'b0011001} ; // 7-seg for E
     4'hf: {hex_1, hex_0} = {7'b1111001, 7'b0010010} ; // 7-seg for F
  default: {hex_1, hex_0} = {7'b1111001, 7'b1111111} ; // 7-segment code for blank
  endcase   
  end  
  endmodule
 
// top level module counter_hexa
module counter_hexa( enable, clk_50, reset, hex_1, hex_0, clk_out);
input enable, clk_50, reset;
output [7:0] hex_1, hex_0;
output wire clk_out;
 
wire [7:0] out;
 
clock_divide ch_cd(clk_out,clk_50);
up_counter  ch_upc(clk_out, reset, enable, out);
hexadecimalcounter ch_hxdc(out, hex_1, hex_0);
endmodule
 
Here is the code. Hope to hear from you soon.
 
[COLOR="silver"][SIZE=1]- - - Updated - - -[/SIZE][/COLOR]
 
sorry, there is a slight change in up counter module, i commented it out...so here is the new code
 
module up_counter( out, enable , clk, reset );
output [7:0] out;
input enable, reset, clk;
reg [7:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin
out <= 8'h0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule

muzammil007 said:

) clock_divide ch_cd(clk_out,clk_50);
up_counter ch_upc(clk_out, reset, enable, out);

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aruipksni said:

up_counter ch_upc(clk_out, reset, enable, out);.

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YEAR_ said:

should be up_counter ch_upc(out,enable ,clock_out ,reset)

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aruipksni said:

your port mapping is incorrect.
try "Modules connected by name" as you were advised.

Click to expand...

muzammil007 said:

no..what i am trying to do so is that i have my output clk_out, which is actually a slow clock, in order to see my counter counting from 00 to FF. So i have designed these three modules. The output of clock_divide will serve as clock input to my counter block.

- - - Updated - - -



I did it as you advised but still i am unable to see any output.
Should i forward you the code again ?

Click to expand...

aruipksni said:

1. mappings :
clock_divide ch_cd(clk_out,clk_50);
up_counter ch_upc(out,enable ,clk_out ,reset);
hexadecimalcounter ch_hxdc(hex_1, hex_0, out);

2. use correct vector size :
module hexadecimalcounter(hex_1, hex_0, hex_num);
input [3:0] hex_num;
output[7:0] hex_1;
output[7:0] hex_0;
reg [7:0] hex_1;
reg [7:0] hex_0;

also in top :
wire [3:0] out;

3. add init , keep size correct :

module up_counter( out, enable , clk, reset );
output [3:0] out;
input enable, reset, clk;
reg [3:0] out;
//-------------Code Starts Here-------
initial begin
out=4'h0;
end
always @(posedge clk)
if (reset) begin
out <= 4'h0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule

View attachment 94250

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