shaikss
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Hi Folks,
I have designed a rectifier and a regulator as independent entities. Both of these blocks are working fine when simulated in virtuoso independently. But when I integrate them, i.e when I connect regulator to rectifier, I am unable to see regulated output. I have attached the snapshot of rectifier and regulator blocks. For regulator, I have used another circuit to derive reference voltage Vref. Note: I have used 4-stage rectifier for which the current at the output of the rectifier is 2uA. Pls let me know why it is happening so. The first snapshot is the regulator ckt and the second one is reference voltage generator for regulator and the third is single stage rectifier block. I have used 4-stages for the rectifier. I see a regulated output of -0.5 Volts when the rectified dc voltage is saturated to 1Volt.
I have designed a rectifier and a regulator as independent entities. Both of these blocks are working fine when simulated in virtuoso independently. But when I integrate them, i.e when I connect regulator to rectifier, I am unable to see regulated output. I have attached the snapshot of rectifier and regulator blocks. For regulator, I have used another circuit to derive reference voltage Vref. Note: I have used 4-stage rectifier for which the current at the output of the rectifier is 2uA. Pls let me know why it is happening so. The first snapshot is the regulator ckt and the second one is reference voltage generator for regulator and the third is single stage rectifier block. I have used 4-stages for the rectifier. I see a regulated output of -0.5 Volts when the rectified dc voltage is saturated to 1Volt.