recovery time of sync reset vs. async reset

[stanford]

1. for sync reset, we have to time assertion and deassertion of the reset? But for async reset, we only have to time deassertion of the reset right?

2. I'm reading that one of the advantage for sync reset is that it will meet reset recovery time because its synchronous. Don't we have to meet recovery time of the reset for async reset as well?

 

[wwfeldman]

2. I'm reading that one of the advantage for sync reset is that it will meet reset recovery time because its synchronous. Don't we have to meet recovery time of the reset for async reset as well?

yes you do need to meet all the setup, holdup, assert, de-assert etc times.
synchronous reset does meet them

async may not
therefore sometimes strange things happen

 

[stanford]

async may not
therefore sometimes strange things happen

could you explain this a bit more?

we time the deassertion of async resets, so we are good here.
For assertion of async reset, which is not timed, what strange things can happen?

Thanks!

 

[wwfeldman]

let's say the setup and hold times are both 1 time unit
if you meet these conditions, everything works as expected according to the various data sheets for the various parts

if you don't meet one or both, you run into the various race condition possibilities and what happens
is at least a temporary instability in some gate

at worst? maybe a latch up and blue screen of death,
or (for example) a power converter could (conceivably) turn on all of the power switches at the same time
and burn itself up

 

[FvM]

we time the deassertion of async resets, so we are good here.
For assertion of async reset, which is not timed, what strange things can happen?

You are talking about a specific application of asynchronous reset, all registers are reset in common, e.g. a power on reset. In this case, the behavior of register output during reset assertion is irrelevant.

But you might have the idea to apply an asynchronous reset to a submodule of your design while other parts of the circuit are still reading its output. In this case assertion timing can matter.

In other words, the prerequisites of your question aren't clear.

 

[stanford]

But you might have the idea to apply an asynchronous reset to a submodule of your design while other parts of the circuit are still reading its output. In this case assertion timing can matter.

I see. you are saying that since async reset assertion is not timed, flops can go in reset at different times.