Recovery and removal time of async reset

[stanford]

For an active low reset signal that is asserted async, and deasserted synchronously,

1. Does the recovery and removal time apply to only deassertion of the reset (i.e valid only for rising edge of the reset)?
2. If recovery and removal time is violated, output can be metastable. What is happening physically that could cause the metastability?

Thanks!

 

[KlausST]

Hi,

What is happening physically that could cause the metastability?

This is not an unknown phenomenom, thus there are half a million results on an internet search.
Wikipedia, technical descriptions, overviews, how to avoid it...

What else information can we add here?

Klaus

 

[stanford]

Hi,


This is not an unknown phenomenom, thus there are half a million results on an internet search.
Wikipedia, technical descriptions, overviews, how to avoid it...

What else information can we add here?

Klaus

I wanted to know from reset perspective.

For async reset deassertion that fails to meet recovery/removal time, the flop will get the d input when the reset is removed. And let's say D input is meeting timing. Is the concern with a race between the stable d input value vs. reset value at the clk edge?

 

[FvM]

Obviously a timing conflict can only manifest if the next d state is different from reset state. d does not necessarily change near the clock edge of interest. The critical parameter is the relation between reset removal and active clock edge.

As a side remark, the timing violation must not necessarily involve true metastability, most cases of hardware failures due to timing violation are caused by inconsistent sampling of multi-bit entities. E.g. some bits of a counter are hold in reset state while others start to count.