Reciprocal of a std_logic_vector signal.

[champnehsam]

I am using Xilinx for VHDL coding. I have a 8 bit std_logic_vector signal , say inp. I want output = 1*K/ input (where K is a constant.)How do I do this reciprocal division. I am stuck in my code please help.



Regards,
Neharika

 

[Toneski_IP]

The long answer is :- It depends.

What resolution do you require the result to be?
Are you OK with a rounded integer result?
How fast do you need the result? (Single clock, multiple clocks?).
Do you have a spare multiplier in your fabric?

If you can come back with some answers, then I may have some idea's, but be warned - division can be a real pain.

T.

 

[champnehsam]

Ok
I am not doing some big time stuff. I am estimating speed using encoders. So the pulses which I counted are inversely proportional to speed. So i need to inverse the count.
I am ok with rounded integers and Single clock multiple clock ..anything will do.But plz tell me if there is way out. I am just badly stuck over this.