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What are reasonable values for on-chip (planar spiral) inductors in a typical 130nm process? I know that values larger than 100nH are not meaningful because the total length becomes so large that it cannot be considered a lumped element any more at frequencies of interest. I also have some vague feeling that the smallest meaningful inductors are on the other of 500pH but I'm not sure.
Background: I have an optimization for a lumped delay line (~1GHz). I optimize for area and use a first order approximation of Area is proportional to N*L^2 where N is the number of inductors and L the value of each inductor. The result is N=250 (!) with L=360pH each.
Another design point (based on this first order optimization) is N=18 with L=3.52nH each.
Area-wise (and performance wise) the second design point feels more reasonable. I feel the first design point has issues likely with parasitics and mutual coupling of so many inductors (?). Maybe there is a better first-order way to optimize this than Area=N*L^2 ?
Background: I have an optimization for a lumped delay line (~1GHz). I optimize for area and use a first order approximation of Area is proportional to N*L^2 where N is the number of inductors and L the value of each inductor. The result is N=250 (!) with L=360pH each.
Another design point (based on this first order optimization) is N=18 with L=3.52nH each.
Area-wise (and performance wise) the second design point feels more reasonable. I feel the first design point has issues likely with parasitics and mutual coupling of so many inductors (?). Maybe there is a better first-order way to optimize this than Area=N*L^2 ?
