Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
DRC(design rule) violations may be resulted by
- insufficient routing resource, (floorplan, nr. of routing layers),
- type of vias for router,
- ...
-----------------------------------------------------------------------------
Process antenna violation may be caused by
- do not allow diode insertion to fix antenna violation,
- bad routing quality,
- ...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.