[SOLVED] reason behind FDSOI flipwell architectures being low threshold voltage device

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ABwag

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What is the reason behind Flip well architectures in FDSOI ,for example : NMos in Nwell and PMOS in P well are low vt device?How does this architecture makes the device low Threshold voltage device?
 

Typical NMOS is N gate over P sub and the threshold is
kind of the difference of gate / substrate charges, across
dielectric thickness (a biased capacitor, if you will). Using
N on Nwell (or P on psub) reduces this charge-difference
and thus the VT.

Of course there are more sophisticated analyses / models
to be had, but you can get a lot of basic understanding
from the "precharged capacitor" mental model.
 

Hi..
Could you please elaborate on this? nmos in pwell has -vely charged ions under the Box when +ve Vg is applied -that can be seen as increased dielectric width - cap value decreases- charge it can hold decreases . So this has relatively high Vth than nmos in nwell. Am I right?
 

Yes. N poly over Nwell and N+ S/D tends to make a depletion
mode NMOSFET with a negative VT.
 
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