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OK again you have failed to define spec for low impedance and voltage regulation error.

Your design approach is no good.

A) Either define load current max and load regulation error % @ -2.5V

e.g. 1% of 2.5V / 1A =Zo = 25 mohms at DC and rising to ___ at ___ MHz

Or

B) Define Zo at DC, f(max) based on fmax=0.5 / Trise time

A comparator output impedance Zol = output low = Vol/Io with open switch has R pull-up for Zoh

If this is just gate current then DC is negl. and ac current depends on switched Q when Vdd is enabled unless RF is involved on gate input then Ciss Rg +Rs, Vgs swing may be used to  compute gate current.