I'm trying to read in a data file to a spartan 3E starter kit using verilog. The file is simply a list of 8bit binary numbers (eg.11000011). I wish to read each line in one at a time, in order to activate the appropriate LEDs. The code I've written is listed below and uses $fscanf to read in the data. However, when I try to generate the programming file I get the error: "File argument of function $fscanf is not constant."
I am also unsure where exactly to physically place my data file. From the examples I've found eg. "in = $fopen("data.txt","r");" presumably this should be in the same directory as the verilog module file?
module inputdata(outputreg[7:0] leds,inputwire clock,input reset
);integer in, line;reg[47:0] din;reg[23:0] state;initialbegin
in =$fopen("data.txt","r");endalways@(posedge clock ornegedge reset)beginif( reset ==1'b0)begin
state <=24'b0;// Allows the change in LEDs to be seen
leds <=8'b0;endelsebegin
state <= state +24'b1;if( state ==24'hFFFFFE)begin
line =$fscanf(in,"%b",din);// reads in value to be set to LEDendif( state ==24'hFFFFFF)begin
leds <= line;// sets LED valueendendendendmodule
$fscanf is not synthesizable. It is used for testbenches or behavioural models.
If you want to transfer data from a PC , you will have to create a hardware interface in the FPGA that can pull data from the PC and software in the PC to send the data to the FPGA. IIRC the Spartan boards have a USB/UART chip that you can use. You would design a UART in Verilog that talks to the USB/UART device amd then use a PC tool like Hyperterminal or TeraTerm to send the FPGA the data. The USB/UART device will look like a COM port to the terminal emulator.
HI.I want programming synthsizer si4136 with fpga. but I dont know how can I start?the si4136 has three pin for programmig, sclk and SEN and SDATA. IF I DESCRIBE it operation:
when sclk event and sclk=1 and SEN=0 the sdata IS ACTIVE and with edge up sclk=1 a bit of sdata transfer to internal register of si4136.if I want to programming for example reg1 and reg3 and reg6(when is RF operation) .how should I do?
sclk(cycle time)=40ns(minimum)
SEN(PULSE WIDTH)= 10ns(when SEN=1)