reading and writing files in vhdl

hello
i want to read and write a file with vhdl programing...it is firs time to work with files in vhdl...can you help me how do it? what should i do from fist step?
should i add textfile to my project or not? and how identify addres the text file in my code?what should be the format of file?

...........

i find a code and use if but it has error...i think it may be about accessing to file :
please hehp me
thank a lot

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY rom IS
PORT(addr : IN INTEGER ; cs : IN std_logic ; data : OUT INTEGER);
END rom;

ARCHITECTURE rom OF rom IS
BEGIN

PROCESS(addr, cs)
VARIABLE rom_init : BOOLEAN := FALSE; --line 1
TYPE rom_data_file_t IS FILE OF INTEGER; --line 2

FILE rom_data_file : rom_data_file_t IS IN --"rom_data_file.dat"; --line 3


TYPE dtype IS ARRAY(0 TO 63) OF INTEGER;
VARIABLE rom_data : dtype; --line 4
VARIABLE i : INTEGER := 0; --line 5
BEGIN

IF (rom_init = false) THEN --line 6
WHILE (NOT ENDFILE(rom_data_file) AND (i < 64)) LOOP
READ(rom_data_file, rom_data(i)); --line 8
i := i + 1; --line 9
END LOOP;
rom_init := true; --line 10
END IF;

IF (cs = '1') THEN --line 11
data <= rom_data(addr); --line 12
ELSE
data <= -1; --line 13
END IF;

END PROCESS;
END rom;

You want to initialize a signal?
1-In verilog, it is easiest with readmem.
2-you could do it with the simulator command (tcl in general)
3-in vhdl you need to develop code to read file like this:

PROCEDURE ReadWord(VARIABLE InLine: INOUT line; VARIABLE s: OUT string;
VARIABLE OK: INOUT boolean) IS
VARIABLE ch : character;
VARIABLE k : integer;
VARIABLE intOK : boolean;
BEGIN
k:=1;
intOK:=OK;
L1: LOOP
read(InLine,ch,intOK);
EXIT L1 WHEN(ch=';' or not(intOK) or not(ch=HT or ch=' ' or ch=':' or ch=','));
END LOOP;
L2: LOOP
EXIT L2 WHEN (ch=HT or ch=' ' or ch=':' or ch=';' or ch=',' or not(intOK));
s(k):=ch;
k:=k+1;
read(InLine,ch,intOK);
END LOOP;
s(k):=NUL;
OK:=OK and k>0;
END ReadWord;