Reading a library in Tetramax

Hi,

When trying to read a library in Tetramax I got these warnings:

BUILD-T> read_netlist /usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib
Begin reading netlist ( /usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib )...
Error: Line 1 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected "identifier" got "(class) {"). (N1-33)

Error: Line 1 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got "class"). (N1-34)

Error: Line 1 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got ") {"). (N1-35)

Error: Line 1 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got "{"). (N1-36)

Error: Line 3 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got "/* revision 1.5 added latch cell KDC */"). (N1-37)

Error: Line 3 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got "* revision 1.5 added latch cell KDC */"). (N1-38)

Error: Line 3 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got "revision"). (N1-39)

Error: Line 3 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got "1.5 added latch cell KDC */"). (N1-40)

Error: Line 4 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got "/* revision 1.6 made fixes to function statements of XOR and XNOR */"). (N1-41)

Error: Line 4 (/usr/local/synopsys/syn_vE-2010.12-SP4/libraries/syn/class.lib), parsing error (expected ";" got "* revision 1.6 made fixes to function statements of XOR and XNOR */" -- Too many errors; parsing terminated). (N1-42)

Does anyone know why I got these errors and how I can fix it?

Thanks!

TetraMAX uses Verilog library to build fault models.
Try this:
read_netlist /usr/local/synopsys/syn_vE-2010.12-SP4/doc/syn/dft_tutorial/LIB/class.v


From Synopsys.com

Netlist Formats, Testbenches, and Test Patterns Interfaces
TetraMAX ATPG supports popular industry standards for netlist and test pattern formats:
•Circuit netlist: Verilog, VHDL (87 and 93)
•Library: Verilog functional (Structural and UDPs)
•Testbench: Verilog (serial and parallel), VHDL-93 (serial only)
•Test Patterns: STIL, WGL, Verilog VCDE (input only)

Hi there,
"class.lib" is a synopsys format library, it may only contaiin some port timing drive load ... discription.
It is not a simulation model library(functional discription, such as *.v or *.vhd).

Hi kornukhin,

That worked. Thank you so much!!

Also, ic_qiand, thank you for your clarification.