Reading a 2D array of Bit Vector...Please check.

[Mirzaaur]

Hi there,

I am trying to read 2D array using for loop as index to array but index never change from the first vale to next Can you please check where I am wrong ?
as shown:-

library IEEE;
use IEEE.std_logic_1164.all;
use work.my_pack.all;
entity ff is
port( D : in cxt;
clk: in std_logic;
reset: in std_logic;
q: out bit_vector(4 downto 0));
end ff;

architecture behav of ff is
signal check : integer range 0 to 2;
begin

process (clk)

begin
if (clk'event and clk='1') then
for I in 2 downto 0 loop
q <= D(I);
check <= I;

end loop;
end if;
end process;
end behav;



--------------------- cxt is the type, i declared in different file as my pack
package my_pack is
type cxt is array (0 to 2) of bit_vector (4 downto 0);
end package my_pack;
--------------------

thanks and best regrads,

mirzaaur

 

[nand_gates]

Checkout the code below.............
Hope this solves ur problem

library IEEE;
use IEEE.std_logic_1164.all;

--------------------- cxt is the type, i declared in different file as my pack
package my_pack is
type cxt is array (0 to 2) of bit_vector (4 downto 0);
end package my_pack;
--------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.my_pack.all;
entity ff is
port( D     : in cxt;
      clk   : in std_logic;
      reset : in std_logic;
      q     : out bit_vector(4 downto 0));
end ff;

architecture behav of ff is
  signal check : integer range 0 to 2;
begin

process (clk, reset)
  variable count : integer range 0 to 2;
begin
  if (reset = '1') then
    count := 0;
  elsif (clk'event and clk='1') then
    count := count + 1;
    q     <= D(count);
    check <= count;
  end if;
end process;
end behav;

 

[Jools]

may be this code

-----------------------------------
package array2D is
type array2D0 is array (15 DOWNTO 0,9 DOWNTO 0) of STD_LOGIC;
end array2D;
-----------------------------------
--
--
function conv_2d21d ( array2d : array2D0; ch_num : integer range 0 to 15)
        return std_logic_vector is
        variable ch_out  : std_logic_vector (9 downto 0);
    begin            
        for i in 0 to 9 loop
          ch_out(i) := array2d(ch_num , i);
        end loop; 
			
        return ch_out;        
    end conv_2d21d;

----
----
signal Ch_in        :array2D0;
signal Ch_out       :std_logic_vector (9 downto 0);
variable  Ch_num    :integer range 0 to 15;

-- test values
Ch_num := 1;
Ch_in     <= (X"01","0000001111"); 

Ch_out(9 downto 0) <= conv_2d21d( Ch_in,Ch_num);

sorry for errors (if you has founded it) I'm write it rapidly
and sorry for my english